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SAN JOSE, Calif .– (COMMERCIAL THREAD) – Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the delivery of the Cadence® Cerebrus ™ Intelligent Chip Explorer, a new machine learning (ML) -based tool that automates and scales digital chip design, enabling customers to efficiently achieve demanding chip design goals. The combination of Cerebrus and the Cadence RTL approval flow gives advanced chip designers, CAD teams and IP developers the ability to improve engineering productivity up to 10x compared to a manual approach while achieving up to 20% power, performance and area (PPA).

With the addition of Cerebrus to the larger digital product portfolio, Cadence offers the industry’s most advanced ML-enabled complete digital workflow from synthesis to implementation and approval. The new tool is cloud-ready and uses highly scalable compute resources from leading cloud providers to quickly meet design requirements across a wide range of markets including consumer, large-scale computing, 5G communications, automotive and mobile. For more information on Cerebrus, please visit

Cerebrus offers customers the following benefits:

  • ML reinforcement: Quickly find workflow solutions that human engineers might not naturally try or explore, improving PPA and productivity.
  • Reuse of the ML model: Automatically apply design learnings to future designs, reducing the time required to achieve better results.
  • Improved productivity: Allows a single engineer to automatically optimize the RTL to full GDS stream for many blocks simultaneously, allowing entire design teams to be more productive.
  • Massively distributed computing: Provides scalable design exploration on premise or in the cloud for faster workflow optimization.
  • Easy to use interface: A powerful user cockpit enables interactive analysis of results and run management to gain valuable insight into design metrics.

“Previously, design teams did not have an automated way to reuse historical design knowledge, resulting in excessive time spent on manual relearning with each new project and wasted margins,” said Dr. Chin-Chi Teng , senior and general vice president responsible for the Digital & Signoff group at Cadence. “The delivery of Cerebrus marks a revolution in the EDA industry with ML-driven digital chip design where engineering teams have a greater opportunity to have greater impact in their organizations as they can offload manual processes. . As the industry continues to evolve into advanced nodes and the size and complexity of design increases, Cerebrus enables designers to achieve PPA goals much more efficiently.

Cerebrus is part of Cadence’s larger complete digital workflow, working seamlessly with Genus ™ Synthesis Solution, Innovus ™ Delivery System, Tempus ™ Timing Approval Solution, Joules ™ Power Solution RTL, the Voltus ™ IC power integrity solution and the Pegasus ™ verification system to provide customers with a rapid path to design closure and improved predictability. The new tool and the larger flow support the company’s Intelligent System Design ™ strategy, which enables ubiquitous intelligence for design excellence.

Customer endorsements

“To effectively maximize the performance of new products that use emerging process nodes, the digital implementation flows used by our engineering team must be continuously updated. Automated design flow optimization is essential to achieve product development at a much higher throughput. Cerebrus, with its innovative ML capabilities, and Cadence RTL-to-signoff tools provided automated flow optimization and floor plan exploration, improving design performance by more than 10%. Following this success, the new approach will be adopted in the development of our latest design projects.

– Satoshi Shibatani, Director, Department of Digital Design Technology, Shared EDA R&D Division, Renesas

“As Samsung Foundry continues to deploy up-to-date process nodes, the effectiveness of our Design Technology Co-Optimization (DTCO) program is very important and we are always looking for innovative ways to go beyond the PPA in the implementation. implemented chips. As part of our long-term partnership with Cadence, Samsung Foundry has used Cerebrus and the Cadence digital implementation flow on multiple applications. We have seen a power reduction of over 8% on some of our most critical blocks in just a few days compared to several months of manual effort. In addition, we are using Cerebrus for the automated sizing of the ground power distribution network, which has resulted in a more than 50% improvement in the final design schedule. Thanks to Cerebrus and the digital implementation flow delivering better PPA and significant productivity improvements, the solution has become a valuable addition to our DTCO program.

– Sangyun Kim, Vice President, Design Technology, Samsung Foundry

About Cadence

Cadence is a pivotal leader in electronics design, drawing on over 30 years of computer software expertise. The company applies its underlying intelligent systems design strategy to deliver software, hardware and IP properties that turn design concepts into reality. Cadence customers are the most innovative companies in the world, providing extraordinary electronic products, from chips to boards to systems for the most dynamic applications in the market, including consumer computing, large-scale computing. , 5G communications, automotive, mobile telephony, aerospace, industry and health. For seven years in a row, Fortune magazine has named Cadence one of the Top 100 Companies to Work For. Learn more at

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